An Automatic Design Flow from Formal Models to FPGA
نویسنده
چکیده
SMV [McM93] is a language suitable for integrated circuit design and optimized for formal verification. VHDL [IEE93] is a design format suitable for simulation and synthesis, but poorly designed for formal verification purposes. The contribution of this paper is the integration of the two approaches through the definition of systematic rules to translate SMV programs into VHDL descriptions, providing thus an important component for an automated circuit design environment making efficient use of formal methods. Moreover, our translation process targets a synthesis-specific subset of VHDL language. Consequently, the produced VHDL descriptions may be automatically mapped to standard FPGA devices using commercial synthesis tools.
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